Architecture studies performed with IDaSS

A large number of IDaSS designs were not converted (directly) into an ASIC layout. Some of the larger projects are listed below:

Superscalar processors

These can execute more than a single instruction per clock. A design has been made which can execute up to 4 instructions in parallel.

Distributed Programmable Logic Controller

This design allows the interconnection of up to 32 processing units. Special hardware makes them behave as if they are executing a single program. The target processing speed is 600 million operations per second.

Dataflow processors

These simulate a network of interconnected processing nodes. A superscalar version of the NEC uPD7281 device has been designed incorporating 3 parallel calculating units and 4 parallel data token routing and storage pipelines.

Input/output coprocessor

This design was intended to be capable of supporting a large number of external devices by running programs for each of them (with hardware multitasking). Using a single instruction, each of these programs can start built-in Direct Memory Access hardware to transfer data at high speed, after which the program simply continues.

Single chip multi-microprocessor

This design incorporates a set of identical RISC processors and a number of shared co-processors for executing complex instructions. Instruction and result routing matrices connect the two types of processors. One of the co-processors performs the basic operations of a multitasking kernel in hardware and dynamically assigns tasks to the RISC cores (based upon task priorities and their status). Inter-task communication is possible with hardware-implemented mailboxes and semaphores. Click on the link labeled 'MuP' in Bart Theelen's homepage for more information.