IDaSS news

This page contains information on important new features added to recent releases, ordered on release date.

September 17, 2003:

Added 'write through' checking capability to IDaSS multiport RAM models. Lots of hardware memory implementations (including 'Block RAM' inside Xilinx FPGA's) do not allow reading a memory location on one port while that same location is written on another port. IDaSS can now detect this error and handle it in a user defined way (from simply returning an 'UNK'-nown value at the reading port to breaking off the simulation). Note that some older designs may now turn out to contain previously undetected bugs!

November 10, 2002:

Extended Xilinx WebPACK Verilog generator to handle bidirectional FPGA pins using the 'split bus' method.

October 15, 2002:

The portable 'parcel' version of IDaSS is now compatible with the new Cincom VisualWorks Smalltalk Version 7.

September 8, 2002:

Extended Xilinx WebPACK Verilog generator to support Spartan-IIE FPGA series (up to IIE/300) in addition to the Spartan-II FPGA series.

July 25, 2002:

Ported IDaSS to Visualworks 5i.4 Smalltalk environment, which should fully support the latest versions of Windows.