IDaSS features

IDaSS is an Interactive Design and Simulation System for digital circuits, targeted towards VLSI and ULSI designs of complex data processing hardware. It's main features are the following:

Graphics to describe system structure

IDaSS describes a design as a hierarchy of schematics (with re-use of complete schematics possible). A schematic contains elements like registers, RAM's, ROM's, combinatorial (ALU-like) 'operators' and associated Finite State Machine controllers. Data transfer is described by drawing lines representing data buses.

Textual languages to describe behaviour

IDaSS uses specially tailored languages to describe the functional behaviour of specific parts of a system (like operators and FSM controllers). These languages are created specifically for the kind of functionality they have to specify, but have a lot of common constructs and are easy to learn (for instance, there are no reserved words).

Completely integrated design and simulation

IDaSS simulates while designing. Placing an element on a schematic immediately simulates its behaviour. Saving a textual description immediately compiles this into behaviour and simulates it. There is no need to restart simulation if a design error is found, just fix the error, bring the system into a usable state and continue simulation.

IDaSS can be compared to a very advanced electronic breadboard:

Never shortage of parts, the parts you use are always of the correct size and functionality
Complex parts and wide datapaths form no problem at all
Power-on insertion and removal of parts without destroying anything
Errors lead to a simulation halt, not a blown up device
System operation can be observed through an unlimited supply of test probes
System state can be modified easily using interactive editing facilities

Embedded higher abstraction level 'language'

The basic building blocks in IDaSS comprise an abstraction level comparable to Register Transfer Languages. So-called 'Algorithmic Level' blocks are available for prototyping complex (sub-)systems, finding optimal algorithms and timing or as fast(er) simulating substitutes for already designed hardware (without revealing the actual hardware architecture). They can also be applied to build 'intelligent' test benches which can probe into the system without the need to draw physical connections.

Each Algorithmic Level block can specify and simulate the operation of a complete datapath and associated controller(s) using structured programming language constructs. Basic operations and local data storage primitives are hardware oriented, communication and synchronisation with the register transfer level environment is incorporated in the language. A full suite of debugging facilities is available (including execution stack editing and single stepping). Unlike most debugging environments, specified algorithms may be modified while they are executing (remember, IDaSS integrates design and simulation!). A hidden fuzzy logic system will try to keep the execution state consistent after a change.

Friendly to both novices and experienced designers

IDaSS is completely menu driven and its textual languages are easy to learn. An on-line help system (using the [F1] key) gives detailed information on all the system design elements, embedded languages, windows and (most of the-) menus. Yet, the system is powerful enough to handle very complex designs and allows libraries of reusable components/subsystems to be built. To protect against system crashes, automatic saving of designs at regular intervals is possible.

On-the-fly syntax and semantics checking

IDaSS does not allow any operation which can be regarded a syntax error (like connecting buses of different widths). IDaSS will warn the user if he/she tries to do something which may result in system failure (like asking a system element to perform a function which has not been defined yet).

Advanced debugging facilities

A 'probe-set' can be used to attach test probes to different points in a simulated system. Such a probe-set's values can be made visible in a central window, providing more overview of what is going (wr)on(g) in the system. Test point values can be combined using user-defined expressions which can perform tests for special values (like three-state or overload on a bus).

Probe set values can be used to trigger messages, warnings or breakpoints. It is also possible to record simulation traces to external files in a variety of (user-defined!) formats. This facility is powerful enough to generate complete hardware description language test environments. A planned (but not yet available) feature is the capability to play back an already recorded test vector file to compare different simulation runs.

Direct path to hardware

IDaSS design files can be converted into different hardware description languages (see examples of this conversion in VHDL or Verilog ). The actual language/dialect/target libaries/textual layout/etc. to be generated can be chosen by attaching a so-called 'template file' - actually a large rulebase - to the system. Algorithmic Level blocks can not be converted directly into hardware description language form (yet).

To be able to match IDaSS timing simulation and technology limitations (for instance maximum embedded memory sizes) to a synthesis target library, a 'technology file' can also be attached to the system. This technology file can even be changed during simulation.

It is possible to use several different template files for the same technology file (for instance to switch between different synthesis systems) or use different technology files with a single template (for instance to switch to a new -more aggressively scaled- process).