The following is a partial list of ASIC and FPGA designs created
with IDaSS. More designs have been synthesized using two 'silicon compilers'
(Sagantec ASA and Compass) and the
'WebPACK' FPGA tools, but most of these were for tool testing purposes only.
16 mm2, 1.5um ES2 CMOS, 18 MHz
Takes 1-5 clock cycles per instruction,
averaging 5 Mips (8 times faster than the original Intel design). Designed
by a student in approximately 150 hours.
50 mm2, 1.2um ES2 CMOS, 16 MHz
The telephone exchange switch is non blocking and fault tolerant
by using the (4,2) concept (needs four of these ASIC's in parallel). Designed
by a student in approximately 500 hours, during which time actually two different
architectures were created (the one with the smallest area was synthesized).
15 mm2, 1.0um ES2 CMOS, 50 MHz
This device is capable of encrypting and
decrypting data at a rate of 25 MByte/second. Designed by a student in
less than 150 hours. The actual DES core (logic and 8 lookup table ROM's)
occupies only 6.2 mm2.
28 mm2, 1.0um ES2 CMOS, 7.5 MHz
This device is an 8 bits processor core
compatible with the Intel 8051 processor, but with a 16 Megabyte address
range. Reaches 3.5 Mips average (more than 3 times faster than the original
design at a lower clock frequency). Designed by a student in approximately
0.8 mm2, 0.35um ES2 CMOS, > 50 MHz
This is a specially designed 16 bits embedded
processor core with 4 stage pipeline, which controls the complete data
(de)compression ASIC and also runs a highly irregular part of the time
critical compression algorithms. After very careful architecture design,
IDaSS predicted that the timing of the pipeline stages would be almost perfectly
balanced, a prediction which turned out to be correct in the synthesized
ASIC layout. Designed by a student in approximately 500 hours.
16 mm2, 1.0um ES2 CMOS, 20 MHz
This device is a 4 stage pipelined 8 bits
processor with 1 KWord by 16 bits program ROM and 192 bytes data RAM in
an actual core size of 8 mm2. Reaches
15 Mips with most instructions taking a single clock cycle. Designed in
just three days to check the functionality of the IDaSS-to-Compass VHDL
2001: 'System on a chip' with microcontroller, graphics LCD, A/D, PWM...
Xilinx Spartan-II FPGA, ~40 MHz
Built around a simple 8 bits microprocessor with 512 bytes RAM
and 1 Kilobyte ROM, this system drives a 64x400 monochrome graphics
LCD through a 1 pixel/clock graphics drawing engine. The latter can
draw lines, blocks and ASCII characters with a single command. Also,
the system includes parallel I/O ports, a timer, two pulse width
modulators and two 'delta/sigma' A/D converters (needs one resistor,
one capacitor and an analog voltage comparator as external hardware
for each A/D channel). The processor executes most instructions in a
single clock cycle and reaches 30 MIPS. The total system uses about
80K gates, so it uses ~40% of a Spartan-II/200 FPGA's gates (almost all
the memory blocks of the Spartan-II/200 are used, though). Total design
time was approximately one week.
2002: Intel 8048 series 'construction kit'
Xilinx Spartan-II FPGA, ~35 MHz
This set of modules implements microcontrollers of the Intel
8048 series with a fixed amount of internal RAM (256 bytes) and a
variable amount of program ROM (0.5 .. 4 Kilobyte). Two extra interrupt
inputs are provided and the timer is fitted with a variable prescaler
divider. A variable amount of the 256 bytes 'external' data memory
can be mapped onto additional internal RAM. Connecting the basic
processor core to a specialised interface module and setting an IDaSS
parameter creates the equivalent of an 8041A I/O processor. Separate
modules provide external bus, port 0, ports 1/2 and expander ports 4..7
interfaces (the latter are also available in 8 bits wide versions).
Most instructions execute in the number of clock cycles equal to their
number of bytes, yielding 15..25 MIPS performance (the original reached
0.4 MIPS). With a gate count below 50K, 4 of these cores fit easily in
a Spartan-II/200 FPGA.